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AMCC NPe405L PowerNP Data Sheet
Document Issue 1.00 September 2004
PowerNP NPe405L Data Sheet
COVER
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Features
* PowerNP technology using an IBM PowerPC 405 32-bit RISC processor core operating up to 266 MHz * PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications * External bus for peripheral devices - Flash and ROM interface - Direct support for 8-, or 16-bit SRAM and external peripherals - Up to 4 devices * DMA support for external peripherals, internal UARTs and memory - Scatter-gather chaining supported - Four channels * Two 10/100 Ethernet MACs supporting up to two external PHYs via MII, RMII, or SMII interfaces * HDLC interface with 32 channels through two ports at up to 4.096 Mbps each or 8.192 Mbps for a single port * Programmable interrupt controller - Seven external and 29 internal - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core - Programmable critical interrupt priority ordering - Programmable critical interrupt vector * Programmable timers * Two serial ports (16550 compatible UART) * One IIC interface * General Purpose I/O (GPIO) available * Supports JTAG for board level testing * Internal processor local bus (PLB) runs at SDRAM interface frequency
Description
Designed specifically to address embedded applications, the NPe405L provides a highperformance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, Ethernet EMACs, HDLC controller, external bus controller for ROM, Flash, and peripherals, DMA with scattergather support, serial ports, IIC interface, and general purpose I/O. Technology: IBM CMOS SA-12E 0.25 m (0.18 m Leff) Package: 23mm, 324-ball enhanced plastic ball grid array (E-PBGA) Power (typical): 1.3W at 133MHz, 1.7W at 200MHz, 1.8W at 266MHz
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 HDLCEX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Tables
System Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 I/O Specifications--All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I/O Specifications--133 and 200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O Specifications--266MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figures
NPe405L Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 23mm, 324-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
Processor Frequency 133MHz 133MHz 200MHz 200MHz 266MHz 266MHz Rev Level A A A A A A
Product Name NPe405L NPe405L NPe405L NPe405L NPe405L NPe405L
Order Part Number1 IBM25NPE405L-3FA133C IBM25NPE405L-3FA133CZ IBM25NPe405L-3FA200C IBM25NPe405L-3FA200CZ IBM25NPe405L-3FA266C IBM25NPe405L-3FA266CZ
Package 23mm, 324 E-PBGA 23mm, 324 E-PBGA 23mm, 324 E-PBGA 23mm, 324 E-PBGA 23mm, 324 E-PBGA 23mm, 324 E-PBGA
PVR Value 0x416100C0 0x416100C0 0x416100C0 0x416100C0 0x416100C0 0x416100C0
JTAG ID 0x04247409 0x04247409 0x04247409 0x04247409 0x04247409 0x04247409
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
This section provides the part numbering nomenclature for the NPe405L. For availability, contact your local IBM sales office. The part number contains a part modifier. This modifier provides for identification of future enhancements (for example, higher performance). Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the NPe405L User's Manual for details on the register content.
IBM Part Number Key
IBM25NPe405L-3FA200Cx
Shipping Package Blank = Tray Z = Tape and reel IBM Part Number Grade 3 Reliability Operational Case Temperature Range (-40C to +85C) Processor Speed 133MHz 200MHz 266MHz Revision Level
Package (E-PBGA)
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
NPe405L Embedded Controller Functional Block Diagram
Universal Interrupt Controller x2 Clock Control Reset Timers MMU PPC405 Processor Core JTAG 8KB D-Cache DCU Trace ICU 16KB I-Cache Arb On-chip Peripheral Bus (OPB) GPIO IIC UART x2 Power Mgmt DCRs
See Peripheral Interface Clock Timing table
DCR Bus
DMA Controller (4-Channel)
OPB Bridge
Processor Local Bus (PLB) Ethernet x2 HDLCEX
MAL0
MAL1 SDRAM Controller 13-bit addr 32-bit data External Bus Controller 28-bit addr 16-bit data
ZMII
Two 32-channel ports
MII, RMII, SMII
The NPe405L is designed using the IBM Microelectronics Blue Logic methodology in which major functional blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way to generate complex ASICs using IBM CoreConnect Bus Architecture.
Address Map Support
The NPe405L incorporates two separate address maps. The first is a fixed processor address map that serves the PowerPC family of processors. This address map defines the possible contents of various address regions which the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the NPe405L processor through the use of mtdcr and mfdcr commands.
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
System Address Map 4GB Total System Memory
Function Subfunction Start Address 0x00000000 SDRAM, External peripherals Note: Any of the address ranges listed at right may be use for any of the above functions. 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xEF900000 Boot-up External peripheral bus boot 1 UART0 UART1 IIC0 OPB Arbiter Internal peripherals GPIO0 controller registers GPIO1 controller registers Ethernet MAC 0 registers Ethernet MAC 1 registers ZMII control registers HDLCEX Notes: 1. When external peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. After the boot process, software may reassign the boot memory regions for other uses. 3. All address ranges not listed above are reserved. 0xFFE00000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600780 0xEF600800 0xEF600900 0xEF600C10 0xEF610000 End Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6007FF 0xEF6008FF 0xEF6009FF 0xEF600C1F 0xEF61FFFF Size 3712MB 8MB 44MB 6MB 1MB 263MB 2MB 8B 8B 32B 64B 128B 128B 256B 256B 16B 64KB
General use
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
DCR Address Map 4KB Device Configuration Register
Function DCR address space Reserved Memory controller registers External bus controller registers Reserved PLB registers Reserved OPB bridge-out registers Reserved Clock, control and reset Power management Interrupt controller 0 Interrupt controller 1 Reserved Miscellaneous DMA controller registers Reserved MAL0 registers (Ethernet) MAL1 registers (HDLCEX) Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
1
Start 0x000 0x000 0x010 0x012 0x014 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0D0 0x0E0 0x0F0 0x100 0x140 0x180 0x200 0x280
End 0x3FF 0x00F 0x011 0x013 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B7 0x0BF 0x0CF 0x0DF 0x0EF 0x0FF 0x13F 0x17F 0x1FF 0x27F 0x3FF
Size 1KW (4KB)1 16W 2W 2W 108W 16W 16W 8W 8W 8W 8W 16W 16W 16W 16W 64W 64W 128W 128W 384W
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
SDRAM Memory Controller
The NPe405L Memory Controller provides a low latency access path to SDRAM memory. The memory controller supports four logical banks. Up to 256MB per bank are supported, for a maximum of 1GB total. Memory access and refresh timing, address and bank sizes, and memory addressing modes are programmable. Features include: * 11x8 to 13x11 row-column address modes (2- and 4-bank devices supported) * Memory bus operates at same frequency as PLB * 32-bit memory interface support * Programmable address range for each bank of memory - 4GB address space * Industry standard 168-pin DIMMS are supported (some configurations) * 200 MHz NPe405H supports up to 100 MHz memory with PC100 support * 266 MHz NPe405H supports up to 133 MHz memory with PC133 support * 4MB to 256MB per bank * Programmable timing * Auto refresh * Page Mode Accesses with up to 4 open pages * Power Management (self-refresh) * Error Checking and Correction (ECC) support - Standard single error correct, double error detect coverage - Aligned nibble error detect - Address error logging
External Bus Controller (EBC)
* Supports four ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported * Up to 66.66MHz operation * Burst and non-burst devices * 8-, 16-bit byte-addressable data bus width support * Latch data on Ready, Synchronous or Asynchronous * Programmable 2K clock-cycle time-out counter with disable for Ready
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
* Programmable access timing per device - 0-255 wait states for non-bursting devices - 0 -31 Burst Wait States for first access and up to 7 Wait States for subsequent accesses - Programmable chip select assertion/negation relative to driving address bus - Programmable output and write-enable assertion/negation relative to assertion of chip select * Programmable address mapping * Peripheral device wait via "Ready"
DMA Controller
* Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers * Four channels * Scatter/Gather capability for programming multiple DMA operations * 8-, 16-, 32-bit peripheral support (OPB and external bus attached) * 32-bit addressing * Address increment or decrement * Internal 32-byte data buffering capability * Supports internal and external peripherals * Support for memory mapped peripherals * Support for peripherals running on slower frequency buses
Serial Interface
* Two 8-pin UART interfaces provided * Selectable internal or external serial clock to allow wide range of baud rates * Register compatibility with NS16550 register set * Complete status reporting capability * Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode * Fully programmable serial-interface characteristics * Supports DMA using internal DMA engine
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
IIC Bus Interface
* Compliant with Phillips(R) Semiconductors I2C Specification, dated 1995 * Operation at 100kHz or 400kHz * 8-bit data * 10- or 7-bit address * Slave transmitter and receiver * Master transmitter and receiver * Multiple bus masters * Supports fixed VDD IIC interface * Two independent 4 x 1 byte data buffers * One programmable interrupt request signal * Provides full management of all IIC bus protocol * Programmable error recovery
HDLCEX Interface
* 32-channel HDLC controller * Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 4.096 Mbps per port or 8.192 Mbps when using a single port * Supports HDLC protocol as well as a Transparent mode * For a single channel per port, autonomous management of I-Frames and S-Frames of the Normal Response mode (NRM) protocol on one channel per port. U-frames are handled by software. * Supports software emulation of NRM on all channels
General Purpose IO (GPIO) Controller
* Most GPIOs are pin-shared with other functions. Configuration registers are provided to determine whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The GPIO function has 32 I/Os. * Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, threestated if output bit is 1)
Universal Interrupt Controller (UIC)
Two cascaded Universal Interrupt Controllers (UICs) provide the control, status, and communications necessary for the interrupt sources and the PowerPC processor. Features include: 10
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
* Seven external and 29 internal interrupts * Edge triggered or level-sensitive * Positive or negative active * Selectable non-critical or critical interrupt requests to the PPC405 processor core * Programmable critical interrupt priority ordering * Programmable critical interrupt vector generation for reduced latency interrupt handling
10/100 Mbps Ethernet MAC
* Two units capable of full- and half-duplex, 10 Mbps or 100 Mbps operation * Integrated ZMII Bridge supports use of MII, SMII or RMII connections to external PHYs (PHYs not included on chip) - Reduced Media Independent Interface (RMII) or Serial Media Independent Interface (SMII) for one to two PHY applications - Media Independent Interface (MII) for single or dual PHY applications * Dedicated media access layer (MAL) provides DMA support
JTAG
* IEEE 1149.1 Test Access Port * Debugger support * JTAG boundary scan support (BSDL file available)
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
23mm, 324-Ball E-PBGA Package
Top View
Gold gate release corresponds to A01 ball location
Note: All dimensions are in mm.
Bottom View
23.0 1.0 0.60 nom 0.30 nom
AB AA Y W V U T R P N M L K J H G F E D C B A
1.0
Thermal balls
23.0
01 03 05 07 09 11 13 15 17 19 21 02 04 06 08 10 12 14 16 18 20 22
0.60 Solder Ball
2.65 max
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal or signals in brackets. Multiplexed signals appear alphabetically multiple times in the list-- once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page 32 where the signals in the indicated interface group begin.
Signals Listed Alphabetically
Signal Name AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 CAS ClkEn0 ClkEn1 [DMAAck0]GPIO13 [DMAAck1]GPIO14 [DMAAck2]GPIO15 [DMAAck3]GPIO16 [DMAReq0]GPIO09 [DMAReq1]GPIO10 [[DMAReq2]GPIO11 [DMAReq3]GPIO12 DQM0 DQM1 DQM2 DQM3 DQMCB ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMC0MDClk EMC0MDIO [EMC0Sync]EMC0TxEn[EMC0Tx0En]
(Part 1 of 11)
Ball H21 AB15 Y14 AA07 Y08 AB06 AA06 AA12 Y13 AA13 U22 U21 T20 D17 P19 T22 T21 R20 U03 U01 R02 L01 AA04 AA05 Y06 AB04 AA03 Y05 AB03 Y04 W06 AB16 AA16 AB21 Ethernet Ethernet Ethernet 32 32 32 SDRAM 33 SDRAM 33 SDRAM 33 External Peripheral Bus 34 External Peripheral Bus 34 SDRAM SDRAM 33 33 SDRAM 33 Power SDRAM Interface Group Page 37 33
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] EMC0TxD2[EMC0Tx1D0] EMC0TxD3[EMC0Tx1D1] EMC0TxEn[EMC0Tx0En][EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC0Tx0En]EMC0TxEn[EMC0Sync] [EMC0Tx1En]EMC0TxErr [EOT0/TC0]GPIO24 [EOT1/TC1]GPIO25 [EOT2/TC2]GPIO26 [EOT3/TC3]GPIO27 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
(Part 2 of 11)
Ball AA22 U19 W20 Y22 AB21 AB20 AB21 AB20 B19 B18 C16 B17 A01 A05 A09 A14 A18 A22 B02 B21 C03 C20 D04 D08 D11 D12 D15 D19 E01 E22 H04 H19 J01 J09-J14 J22 K09-K14 L04 L09-L14 L19 Power Note: J09-J14, K09-K14, L09-L14, M09-M14, N09N14, and P09-P14 are also thermal balls. 37 External Peripheral Bus 34 Ethernet Ethernet Ethernet 32 32 32 Ethernet 32 Interface Group Page
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
(Part 3 of 11)
Ball M04 M09-M14 M19 N09-N14 P01 P09-P14 P22 R04 R19 V01 V22 W04 W08 W11 W12 W15 W19 Y03 Y20 AA02 AA21 AB01 AB05 AB09 AB14 AB18 AB22 Power Note: J09-J14, K09-K14, L09-L14, M09-M14, N09N14, and P09-P14 are also thermal balls. 37 Interface Group Page
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name GPIO00[TrcClk] GPIO01[TS1E]GPIO08[TS6] GPIO02[TS2E] GPIO03[TS1O] GPIO04[TS2O] GPIO05[TS3] GPIO06[TS4] GPIO07[TS5] GPIO08[TS6] GPIO09[DMAReq0] GPIO10[DMAReq1] GPIO11[DMAReq2] GPIO12[DMAReq3] GPIO13[DMAAck0] GPIO14[DMAAck1] GPIO15[DMAAck2] GPIO16[DMAAck3] GPIO17[IRQ0] GPIO18[IRQ1] GPIO19[IRQ2] GPIO20[IRQ3] GPIO21[IRQ4] GPIO22[IRQ5] GPIO23[IRQ6] GPIO24[EOT0/TC0] GPIO25[EOT1/TC1] GPIO26[EOT2/TC2] GPIO27[EOT3/TC3] GPIO28[UART1_DCD][HDLCEXTxEnA] GPIO29[UART1_RI][HDLCEXTxEnB] GPIO30 GPIO31[PerWE] Halt HDLCEXRxClk HDLCEXRxDataA HDLCEXRxDataB HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA HDLCEXTxDataB [HDLCEXTxEnA]GPIO28[UART1_DCD] [HDLCEXTxEnB]GPIO29[UART1_RI] HDLCEXTxFS
(Part 4 of 11)
Ball B20 C18 A20 N20 N22 P21 P20 R22 R21 P19 T22 T21 R20 U22 U21 T20 D17 F20 J20 L21 M21 AA17 AB17 W14 B19 B18 C16 B17 AA15 T01 T03 A13 F22 L20 M22 N21 M20 K20 K21 L22 AA15 T01 K22 System HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel 37 32 32 32 32 32 32 32 System 37 Interface Group Page
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name IICSCL[IECSCL] IICSDA[IECSDA] [IRQ0]GPIO17 [IRQ1]GPIO18 [IRQ2]GPIO19 [IRQ3[GPIO20 [IRQ4[GPIO21 [IRQ5]GPIO22 [IRQ6[GPIO23 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1
(Part 5 of 11)
Ball C17 A19 F20 J20 L21 M21 AA17 AB17 W14 Y12 Y11 AB11 AA11 AA10 Y10 AB10 AA09 Y09 AB08 AA08 W09 AB07 AA14 AB13 SDRAM 33 SDRAM Note: During a CAS cycle MemAddr00 is the least significant bit (lsb) on this bus. 33 Interrupts 36 Interface Group Internal Peripheral Page 35
17
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemDatar07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31
(Part 6 of 11)
Ball AB02 AA01 U04 W03 Y01 V03 Y02 W01 W02 V02 U02 R03 T02 P04 R01 P03 P02 N01 N03 N02 M02 M01 M03 L03 L02 K02 K03 K01 J02 J03 H01 H02 SDRAM Notes: 1. MemData00 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb) Interface Group Page
33
18
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
(Part 7 of 11)
Ball D05 D07 D16 D18 E04 E19 G04 G19 Power T19 T04 V04 V19 W05 W07 W16 W18 37 Interface Group Page
19
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3
(Part 8 of 11)
Ball D06 C04 A03 C05 B03 A04 C06 B04 B05 C07 B06 C08 B07 A07 D09 B08 A08 C09 B09 A10 C10 B10 B11 A11 C11 C12 A12 B12 C15 A17 B14 C14 A15 B15 External Peripheral Bus 34 External Peripheral Bus External Peripheral Bus 34 34 External Peripheral Bus 34 Interface Group Page
20
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerErr PerOE PerPar0 PerPar1 PerR/W PerReady PerWBE0 PerWBE1 [PerWE]GPIO31 PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] [PHY0CrS1DV]PHY0RxDV PHY0RxClk [PHY0RefClk]PHY0TxClk PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] PHY0RxD2[PHY0Rx1D0] PHY0RxD3[PHY0Rx1D1] PHY0RxDV[PHY0CrS1DV] PHY0RxErr[PHY0Rx0Er] [PHY0Rx0Er]PHY0RxErr PHY0TxClk[PHY0RefClk] RAS SysClk SysErr SysReset TCK
(Part 9 of 11)
Ball J04 G01 G02 H03 F01 F02 G03 E02 D02 F03 D01 C02 E03 C01 D03 F04 J21 D14 B01 A02 A16 B16 B13 C13 A13 W17 Y18 Y17 AB19 Y19 Y15 Y16 AA18 AA19 Y17 AA20 AA20 Y19 AB12 G22 C21 A21 J19 Ethernet Ethernet Ethernet Ethernet SDRAM System System System JTAG 32 32 32 32 33 37 37 37 36 Ethernet 32 External Peripheral Bus External Peripheral Bus External Peripheral Bus External Peripheral Bus External Peripheral Bus External Peripheral Bus External Peripheral Bus Ethernet Ethernet Ethernet Ethernet Ethernet 34 34 34 34 34 34 34 32 32 32 32 32 External Peripheral Bus Note: PerData00 is the most significant bit (msb) on this bus. 34 Interface Group Page
21
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name [TC0/EOT0]GPIO24 [TC1/EOT1]GPIO25 [[TC2/EOT2]GPIO26 [TC3/EOT3]GPIO27 TDI TDO TestEn TmrClk TMS [TrcClk]GPIO00 TRST [TS1E]GPIO01 [TS2E]GPIO02 [TS1O]GPIO03 [TS2O]GPIO04 [TS3]GPIO05 [TS4]GPIO06 [TS5]GPIO07 [TS6]GPIO08 UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_CTS [UART1_DCD]GPIO28[HDLCEXTxEnA] UART1_DSR UART1_DTR [UART1_RI]GPIO29[HDLCEXTxEnB] UART1_RTS UART1_Rx UART1_Tx UARTSerClk
(Part 10 of 11)
Ball B19 B18 C16 B17 G21 F21 H20 D20 E21 B20 H22 C18 A20 N20 N22 P21 P20 R22 R21 B22 C19 A06 G20 D22 D21 C22 F19 W22 AA15 W21 U20 T01 V21 V20 Y21 E20 Internal Peripheral 35 Internal Peripheral 35 Trace 37 JTAG JTAG System System JTAG Trace JTAG Trace Trace 36 36 37 37 36 37 36 37 37 External Peripheral Bus 34 Interface Group Page
22
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name VDD VDD VDD VDD VDD VDD VDD VDD WE
(Part 11 of 11)
Ball D10 D13 K19 K04 Power N19 N04 W10 W13 Y07 SDRAM 33 37 Interface Group Page
23
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Signal Name GND PerPar1 PerAddr06 PerAddr09 GND UART0_DSR PerAddr17 PerAddr20 GND PerAddr23 PerAddr27 PerAddr30 GPIO31[PerWE] GND PerCS2 PerR/W PerClk GND IICSDA[IECSDA] GPIO02[TS2E] SysReset GND Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 PerPar0 GND PerAddr08 PerAddr11 PerAddr12 PerAddr14 PerAddr16 PerAddr19 PerAddr22 PerAddr25 PerAddr26 PerAddr31 PerWBE0 PerCS0 PerCS3 PerReady GPIO27[EOT3/TC3] GPIO25[EOT1/TC1] GPIO24[EOT0/TC0] GPIO00[TrcClk] GND UART0_CTS
(Part 1 of 6)
Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 Signal Name PerData13 PerData11 GND PerAddr05 PerAdd7 PerAddr10 PerAddr13 PerAddr15 PerAddr21 PerAddr24 PerAddr28 PerAddr29 PerWBE1 PerCS1 PerBLast GPIO26[EOT2/TC2] IICSCL[IECSCL] GPIO01[TS1E] UART0_DCD GND SysErr UART0_Rx Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 Signal Name PerData10 PerData08 PerData14 GND OVDD PerAddr04 OVDD GND PerAddr18 VDD GND GND VDD PerOE GND OVDD GPIO16[DMAAck3] OVDD GND TmrClk UART0_RTS UART0_RI
Signal Name
24
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 Signal Name GND PerData07 PerData12 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD UARTSerClk TMS GND Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 PerData04 PerData05 PerData09 PerData15 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball UART0_Tx GPIO17[IRQ0] TDO Halt
(Part 2 of 6)
Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 Signal Name PerData01 PerData02 PerData06 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD UART0_DTR TDI SysClk Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 Signal Name MemData30 MemData31 PerData03 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND TestEn AVDD TRST
Signal Name
25
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 Signal Name GND MemData28 MemData29 PerData00 No ball No ball No ball No ball GND GND GND GND GND GND No ball No ball No ball No ball TCK GPIO18[IRQ1] PerErr GND Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 MemData27 MemData25 MemData26 VDD No ball No ball No ball No ball GND GND GND GND GND GND No ball No ball No ball No ball VDD HDLCEXTxClk HDLCEXTxDataA HDLCEXTxFS
(Part 3 of 6)
Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 Signal Name DQM3 MemData24 MemData23 GND No ball No ball No ball No ball GND GND GND GND GND GND No ball No ball No ball No ball GND HDLCEXRxClk GPIO19[IRQ2] HDLCEXTxDataB Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 Signal Name MemData21 MemData20 MemData22 GND No ball No ball No ball No ball GND GND GND GND GND GND No ball No ball No ball No ball GND HDLCEXRxFS GPIO20[IRQ3] HDLCEXRxDataA
Signal Name
26
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 Signal Name MemData17 MemData19 MemData18 VDD No ball No ball No ball No ball GND GND GND GND GND GND No ball No ball No ball No ball VDD GPIO3[TS1O] HDLCEXRxDataB GPIO4[TS2O] Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 GND MemData16 MemData15 MemData13 No ball No ball No ball No ball GND GND GND GND GND GND No ball No ball No ball No ball GPIO09[DMAReq0] GPIO06[TS4] GPIO05[TS3] GND
(Part 4 of 6)
Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 Signal Name MemData14 DQM2 MemData11 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND GPIO12[DMAReq3] GPIO08[TS6] GPIO07[TS5] Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Signal Name GPIO29[UART1_RI] [HDLCEXTxEnB] MemData12 GPIO30 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD GPIO15[DMAAck2] GPIO11[DMAReq2] GPIO10[DMAReq1]
Signal Name
27
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 Signal Name DQM1 MemData10 DQM0 MemData02 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 GND MemData09 MemData05 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball
(Part 5 of 6)
Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Signal Name MemData07 MemData08 MemData03 GND OVDD ECC7 OVDD GND MemAddr11 VDD GND GND VDD GPIO23[IRQ6] GND Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Signal Name MemData04 MemData06 GND ECC6 ECC4 ECC1 WE BankSel1 MemAddr08 MemAddr05 MemAddr01 MemAddr00 ClkEn0 BA1 PHY0RxD0 [PHY0Rx0D0] [PHY0Rx0D] PHYRxD1 [PHY0Rx0D1] [PHY0Rx1D] PHY0RxDV [PHY0CrS1DV] PHY0CrS [PHY0CrS0DV] PHY0TxClk [PHY0RefClk] GND UART1_Tx EMC0TxD3 [EMC0Tx1D1]
Signal Name
U16 U17 U18 U19 U20 U21 U22
No ball No ball No ball EMC0TxD1 [EMC0Tx0D1] [EMC0Tx1D] UART1_DTR GPIO14[DMAAck1] GPIO13[DMAAck0]
V16 V17 V18 V19 V20 V21 V22
No ball No ball No ball OVDD UART1_Rx UART1_RTS GND
W16 W17 W18 W19 W20 W21 W22
OVDD PHY0Col[PHY0Rx1Er] OVDD GND EMC0TxD2 [EMC0Tx1D0] UART1_DSR UART1_CTS
Y16 Y17 Y18 Y19 Y20 Y21 Y22
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 Signal Name MemData01 GND ECC3 DQMCB ECC0 BankSel3 BankSel0 MemAddr10 MemAddr07 MemAddr04 MemAddr03 CAS ClkEn1 MemClkOut0 GPIO28[UART1_DCD] [HDLCEXTxEnA] EMC0MDIO GPIO21[IRQ4] PHY0RxD2 [PHY0Rx1D0] PHY0RxD3 [PHY0Rx1D1] PHY0RxErr [PHY0Rx0Er] GND EMC0TxD0 [EMC0Tx0D0] [EMC0Tx0D] Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 GND MemData00 ECC5 ECC2 GND BankSel2 MemAddr12 MemAddr09 GND MemAddr06 MemAddr02 RAS MemClkOut1 GND BA0 EMC0MDClk GPIO22[IRQ5] GND PHY0RxClk EMC0TxErr [EMC0Tx1En] EMC0TxEn [EMC0Tx0En] [EMC0Sync] GND
(Part 6 of 6)
Ball Signal Name Ball Signal Name
Signal Name
AA22
AB22
29
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Description
The following table provides a summary of the number of package pins (balls) associated with each functional interface group.
Pin Summary
Group
Nonmultiplexed Signals Multiplexed Signals Total Signal Pins AVDD OVDD VDD Gnd Gnd (and thermal) Reserved Total Pins
No. of Pins
167 48 215 1 16 8 48 36 0 324
Multiplexed pins In the table "Signal Functional Description" on page 32, each external signal is listed along with a short description of the signal function. The signals are grouped together according to their function. Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In most cases, the signal name is shown in this table unaccompanied by multiplexed signal names that may be associated with it. In cases where multiplexed signals are in the same functional group, the names appear as a default signal followed by secondary signals in square brackets (for example, EMC0TxErr[EMC0Tx1En]). Active-low signals (for example, RAS) are marked with an overline. Any signal that is not the primary (default) signal on a multiplexed pin is shown in square brackets. The active signal on a multiplexed pin is controlled by programming. It is expected that in any single application, a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Initialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Initialization" on page 51). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Pull-up and Pull-down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V (10k to +5V can be used on 5V tolerant I/Os) and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the NPe405L. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the NPe405L requires only the pull-up and pull-down terminations as specified in the "Signal Functional Description" on page 32, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral and SDRAM bus should be configured and terminated as follows: * Peripheral interface--PerAddr00:31, PerData00:31, and all of the control signals are driven by default. Terminate PerReady high and PerError low. * SDRAM--Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the NPe405L to actively drive all of the SDRAM address, data, and control signals. External Peripheral Bus Control Signals All external peripheral bus control signals (PerCS0:3, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerNP NPe405L Embedded Processor User's Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the NPe405L. Please see "Signals Listed Alphabetically" on page 13 for the pin number to which each signal is assigned. In cases where a multiplexed signal (indicated by the square brackets) is shown without the other signals that are assigned to that pin, you can see what the other signals are by referring to the same table.
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part 1 of 6) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 31.
Signal Name Description I/O Type
Notes
HDLCEX Interface
HDLCEXTxClk HDLCEXTxFS HDLCEXTxDataA HDLCEXTxDataB HDLCEXRxClk HDLCEXRxFS HDLCEXRxDataA HDLCEXRxDataB [HDLCEXTxEnA] [HDLCEXTxEnB] Transmit Clock Transmit Frame Synchronization Transmit Data port A Transmit Data port B Receive Clock Receive Frame Synchronization Receive Data port A Receive Data port B Transmit Enable port A Transmit Enable port B I I O O I I I I O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Ethernet Interface
EMC0MDClk Management Data Clock. The MDClk is sourced to the PHY. Management information is transferred synchronously with respect to this clock (MII, RMII, and SMII). Management Data Input/Output is a bidirectional signal between the Ethernet controller and the PHY. It is used to transfer control and status information (MII, RMII, and SMII). O 3.3V LVTTL
EMC0MDIO
I/O
5V tolerant 3.3V LVTTL
1, 4
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] Transmit Data. A nibble wide data bus towards the net. EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] The data is synchronous with PHY0TxClk EMC0TxD2[EMC0Tx1D0] (MII 0[RMII 0, 1][SMII 0, 1]). EMC0TxD3[EMC0Tx1D1] Transmit Enable. This signal is driven by EMAC2 to the PHY. Data is valid during the active state of this signal. Deassertion of this signal indicates end of frame EMC0TxEn[EMC0Tx0En][EMC0Sync] transmission. This signal is synchronous with PHYTxClk (MII 0[RMII 0]). or SMII Sync. Transmit Error. This signal is generated by the Ethernet controller, is connected to the PHY and is synchronous with the PHY0TxClk. It informs the PHY that an error was detected (MII 0). or Transmit Enable [RMII 1].
O
3.3V LVTTL
O
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
O
3.3V LVTTL
32
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part 2 of 6) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 31.
Signal Name Description Collision [receive error] signal from the PHY. This is an asynchronous signal (MII 0). or Receive Error ([RMII 1]). Carrier Sense signal from the PHY. This is an asynchronous signal (MII 0). or Carrier sense data valid ([RMII 0]). Receiver medium clock. This signal is generated by the PHY (MII 0). I/O Type 5V tolerant 3.3V LVTTL
Notes
PHY0Col[PHY0Rx1Er]l
I
PHY0CrS[PHY0CrS0DV]
I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1, 5
PHY0RxClk
I
1, 4
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] Received Data. This is a nibble wide bus from the PHY. PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] The data is synchronous with PHY0RxClk PHY0RxD2[PHY0Rx1D0] (MII 0[RMII 0, 1][SMII 0, 1]). PHY0RxD3[PHY0Rx1D1] Receive Data Valid. Data on the Data Bus is valid when this signal is activated. Deassertion of this signal indicates end of the frame reception (MII 0). or Carrier sense data valid ([RMII 1]) Receive Error. This signal comes from the PHY and is synchronous with PHY0RxClk (MII 0 [RMII 0]). Transmit medium clock. This signal is generated the PHY ([MII 0]). or Reference Clock [RMII and SMII].
I
1, 4
PHY0RxDV[PHY0CrS1DV]
I
5V tolerant 3.3V LVTTL
1, 5
PHY0RxErr[PHY0Rx0Er]
I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1, 5
PHY0TxClk[PHY0RefClk]
I
1, 4
SDRAM Interface
Memory Data bus Notes: 1. MemAddr00 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory Address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr00 is the least significant bit (lsb). Bank Address supporting up to 4 internal banks Row Address Strobe. Column Address Strobe. DQM for byte lane 0 (MemAddr00:7), 1 (MemAddr08:15), 2 (MemData16:23), and 3 (MemData24:31) DQM for ECC check bits.
MemAddr00:31
I/O
3.3V LVTTL
MemAddr12:00
O
3.3V LVTTL
BA1:0 RAS CAS
O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
O
3.3V LVTTL
DQMCB
O
3.3V LVTTL
33
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part 3 of 6) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 31.
Signal Name ECC0:7 BankSel0:3 WE ClkEn0:1 MemClkOut0:1 ECC check bits 0:7. Select up to four external SDRAM banks. Write Enable. SDRAM Clock Enable. Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attachment without requiring this signal to be repowered by a PLL or zero-delay buffer. Description I/O I/O O O O O Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Notes
External Peripheral Bus Interface
PerData00:15 External peripheral data bus . Note: PerData00 is the most significant bit (msb) on this bus. External peripheral address bus . External peripheral byte parity signals. Peripheral write-bte enable. Byte-enables which are valid for an entire cycle or write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. Used by either external bus controller or DMA controller depending upon the type of transfer involved. Peripheral write enable. Low when any of the two PerWBE signals are low. Peripheral Chip Selects Peripheral output enable. Used by either the external bus controller or the DMA controller depending upon the type of transfer involved. When the NPe405L is the bus master, it enables the peripherals to drive the bus. Peripheral read/write. Used by either the external bus controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1 1
PerAddr04:31 PerPar0:1
O I/O
PerWBE0:1
O
5V tolerant 3.3V LVTTL
2, 7
[PerWE] PerCS0:3
I/O O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
7
PerOE
O
7
PerR/W
O
5V tolerant 3.3V LVTTL
PerReady PerBLast PerClk PerErr
Indicates peripheral is ready to transfer data. Peripheral burst last. Used to indicate the last transfer of a memory access. Peripheral Clock. Used by synchronous peripherals. Used to indicate errors from peripherals.
I O O I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1 7
1, 5
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part 4 of 6) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 31.
Signal Name Description DMA request. Used by peripherals to request a data transfer. Following a system reset, the default mode of the signals is active-low. They may be programmed to activehigh using the DMA0_POL register. DMA acknowledge. Used to indicate to peripherals that data transfer is complete. Following a system reset, the default mode of the signals is active-low. They may be programmed to active-high using the DMA0_POL register. End Of Transfer/Terminal Count. Indication by peripherals that all data has been transfered, or by DMA controller that programmed amount of data has been transfered. Following a system reset, the default mode of the signals is active-low. They may be programmed to active-high using the DMA0_POL register. I/O Type 5V tolerant 3.3V LVTTL
Notes
[DMAReq0:3]
I
1
[DMAAck0:3]
O
5V tolerant 3.3V LVTTL
[EOT0:3/TC0:3]
I/O
5V tolerant 3.3V LVTTL
1
Internal Peripheral Interface
Serial Clock used to provide an alternative clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either or both UART0 and UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Set Ready. UART0 Clear To Send. UART0 Data Terminal Ready. UART0 Request To Send. UART0 Ring Indicator. 5V tolerant 3.3V LVTTL
UARTSerClk
I
1
UART0_Rx UART0_Tx [UART0_DCD] [UART0_DSR] [UART0_CTS] [UART0_DTR] [UART0_RTS] [UART0_RI]
I O I I I O O I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL r
1
1 1 1
1
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part 5 of 6) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 31.
Signal Name UART1_Rx UART1_Tx [UART1_DCD] [UART1_DSR] [UART1_CTS] [UART1_DTR] [UART1_RTS] [UART1_RI] IICSCL IICSDA UART1 Receive data. UART1 Transmit data. UART1 Data Carrier Detect. UART1 Data Set Ready. UART1 Clear To Send. UART1 Data Terminal Ready. UART1 Request To Send. UART1 Ring Indicator. IIC Serial Clock. IIC Serial Data. Description I/O I O I I I O O I I/O I/O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
1 6 1, 4 1, 4 1, 4 6 6 1, 4 1, 2 1, 2
Interrupts Interface
[IRQ0:6] Interrupt Requests. I 5V tolerant 3.3V LVTTL 1
JTAG Interface
TDI TMS TDO TCK TRST Test Data In. Test Mode Select. Test Data Out. Test Clock. Test Reset. TRST must be low at power-on to reset the JTAG boundary scan state machine. I I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 5 1, 4 1, 4
36
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part 6 of 6) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 3. Must pull down. See "Pull-up and Pull-down Resistors" on page 30 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Peripheral Bus Control Signals" on page 31.
Signal Name Description I/O Type
Notes
System Interface
SysClk SysReset SysErr Halt GPIO00:31 TestEn Main System Clock input. Main System Reset. Set to 1 when a Machine Check is generated. Halt from external debugger. General Purpose I/O. To access this function, software must toggle a DCR bit. Test Enable. Used only for manufacturing tests. Pull down for normal operation. This input must toggle at a rate of less than one half the CPU core frequency (less than 100MHz in most cases). In most cases this input toggles much slower (in the 1MHz to 10MHz range). I I/O O I I/O I 3.3V Analog Wire w/ESD 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 3.3V LVTTL Rcvr w/PD 5V tolerant 3.3V LVTTL 1 1 1, 2
TmrClk
I
1
Trace Interface [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6] Even Trace execution status.To access this function, software must toggle a DCR bit. Odd Trace execution status. To access this function, software must toggle a DCR bit. Trace Status. To access this function, software must toggle a DCR bit. Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit. O O O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
[TrcClk]
O
Power Pins
GND VDD OVDD AVDD Ground Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, and P09-P14 are also thermal balls. Logic voltage--2.5V Output driver voltage--3.3V Filtered PLL voltage--2.5V I I I I Hardwire Hardwire Hardwire 3.3V DC Wire w/ESD
Other Pins
Reserved Do not connect signals, voltage, or ground to these pins. n/a n/a
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) PLL Supply Voltage 2 Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Notes: 1. All voltages are specified with respect to ground (GND). 2. AVDD should be derived from VDD using the following circuit: Symbol VDD OVDD AVDD VIN VIN TSTG TC Value 0 to +2.7 0 to +3.6 0 to +2.7 -0.6 to (OVDD + 0.6) -0.6 to (OVDD + 2.4) -55 to +150 -40 to +120 Unit V V V V V
C C
VDD L1
AVDD
L1 - 2.2H SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S) C1 - 3.3 F SMT tantalum C2 - 0.1F SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 - 0.01 F SMT monolithic ceramic capacitor with X7R dielectric or equivalent
C1
C2
C3
Package Thermal Specifications
The NPe405L is designed to operate within a case temperature range of -40C to 85C. Thermal resistance values for the E-PBGA packages in a convection environment are as follows: Airflow ft/min (m/sec)
0 (0) 23mm, 324-balls--Junction-to-Case 23mm, 324-balls--Case-to-Ambient Notes: 1. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax - PxJC, where TJ Max is maximum junction temperature and P is power consumption.
1
Package--Thermal Resistance
Symbol
Unit
200 (1.02) 2 14 C/W C/W
100 (0.51) 2 15
JC CA
2 17
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Parameter Logic Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Logic High (3.3V LVTTL receivers) Input Logic High (2.5V CMOS receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Low Output Logic High Output Logic Low 3.3V I/O input current (no pull-up or pull-down) Input Current (with internal pulldown) Input Current (with internal pull-up) Input Max Allowable Overshoot (2.5V CMOS receivers) Input Max Allowable Overshoot (3.3V LVTTL receivers) Input Max Allowable Overshoot (5.0V LVTTL receivers) Input Max Allowable Undershoot (3.3V or 5.0V receivers) Output Max Allowable Overshoot (3.3V or 5.0V receivers) Output Max Allowable Undershoot (3.3V and 5.0V receivers) Case Temperature Notes:
Symbol VDD OVDD AVDD VIH VIH VIH VIL VOH VOL IIL1 IIL2 IIL3 VIMAO25 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 TC
Minimum +2.3 +3.0 +2.3 +2.0 +1.7 +2.0 0 +2.4 0
Typical +2.5 +3.3 +2.5
Maximum +2.7 +3.6 +2.7 OVDD VDD +5.5 +0.8 OVDD +0.4 10
Unit V V V V V V V V V
Notes
A A A
V V V V
10 (@ 0V) -250 (@ 0V)
400 (@ 3.6V) 10 (@ 3.6V) VDD + 0.6 OVDD + 0.6 +5.5
- 0.6
OVDD + 0.3
V V
- 0.6 - 40
+85
C
1. See "5V-Tolerant I/O Input Current" on page 40
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
5V-Tolerant I/O Input Current
100
0 -100 Input Current (A)
-200 -300
-400
-500
-600 -700 0.0 1.0 2.0 3.0 4.0 5.0 Input Voltage (V)
Input Capacitance
Parameter 3.3V LVTTL I/O) 5V tolerant LVTTL I/O RX only pins Symbol CIN1 CIN2 CIN4 Maximum 2.5 3.5 0.75 Unit pF pF pF Notes
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
DC Electrical Characteristics
Parameter Active Operating Current for VDD @ 133MHz Active Operating Current for VDD @ 200MHz Active Operating Current for VDD @ 266MHz Active Operating Current for OVDD @ 133MHz Active Operating Current for OVDD @ 200MHz Active Operating Current for OVDD @ 266MHz Active Operating Current for AVDD Active Operating Power @ 133MHz Active Operating Power @ 200MHz Active Operating Power @ 266MHz Notes: 1. Maximum power is characterized at VDD=2.7V, OVDD=3.6V, TC=85C, across the silicon process (worse case to best case), while running an application designed to maximize power consumption. The maximum power values are measured with the following clock rate combinations: a. CPU=133.33MHz, PLB=66.66MHz, OPB=66.66MHz, EBC=33.33MHz b. CPU=200 MHz, PLB=100MHz, OPB=50MHz, EBC=50MHz c. CPU=266.66MHz, PLB=66.66MHz, OPB=66.66MHz, EBC=33.33MHz Symbol IDD IDD IDD IODD IODD IODD IADD PDD PDD PDD Minimum 444 468 490 17 24 27 5.5 1.1 1.4 1.5 Typical 497 565 590 23 36 44 6 1.3 1.7 1.8 Maximum 543 676 700 36 51 61 6.5 1.61 21 2.11 Unit mA mA mA mA mA mA mA W W W
Test Conditions
Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." AC specifications are characterized at OVDD = 3.00V and TJ = 85C with the 50pF test load shown in the figure at right.
Output Pin 50pF
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Clocking Specifications
Symbol SysClk Input FC TC TCS TCH TCL SysClk clock input frequency SysClk clock period Clock edge stability (phase jitter, cycle to cycle) Clock input high time Clock input low time 25 15 66.66 40 0.15 40% of nominal period 60% of nominal period 40% of nominal period 60% of nominal period MHz ns ns ns ns Parameter Min Max Units
Note: Input slew rate > 2V/ns MemClkOut Output FC TC FC TC FC TC TCH TCL Other Clocks FC FC FC FC FC FC FC VCO frequency PLB frequency-133MHz PLB frequency-200MHz PLB frequency-266MHz OPB frequency-133MHz OPB frequency-200MHz OPB frequency-266MHz 400 800 66.66 100 133.33 501 50 501 MHz MHz MHz MHz MHz MHz MHz MemClkOut clock output frequency-133MHz MemClkOut clock period-133MHz MemClkOut clock output frequency-200MHz MemClkOut clock period-200MHz MemClkOut clock output frequency-266MHz MemClkOut clock period-266MHz Clock output high time Clock output low time 7.5 45% of nominal period 55% of nominal period 45% of nominal period 55% of nominal period 10 133.33 15 100 66.66 MHz ns MHz ns MHz ns ns ns
Notes: 1. If HDLCEX is not used, the maximum OPB frequency is 66.66MHz.
Clocking Waveform
2.0V 1.5V 0.8V TCH TC TCL
42
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the NPe405L. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the NPe405L the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the NPe405L with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board NPe405L peripherals impose more stringent requirements (see Note 1). * Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. * Use the SDRAM MemClkOut since it also tracks the modulation. Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for additional details. This application note is available on the IBM Microelectronics web site at http://www.chips.ibm.com. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the NPe405L meets the above requirements and does not adversely affect other aspects of the system.
43
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter EMC0MDClk output frequency EMC0MDClk period EMC0MDClk output high time EMC0MDClk output low time PHY0TxClk input frequency PHY0TxClk period PHY0TxClk input high time PHY0TxClk input low time PHY0RxClk input frequency PHY0RxClk period PHY0RxClk input high time PHY0RxClk input low time PerClk output frequency-133MHz PerClk period-133MHz PerClk output frequency-200MHz PerClk period-200MHz PerClk output frequency-266MHz) PerClk period-266MHz PerClk output high time PerClk output low time UARTSerClk input frequency (Note 1) UARTSerClk period UARTSerClk input high time UARTSerClk input low time TmrClk input frequency-133MHz TmrClk period-133MHz TmrClk input frequency-200MHz TmrClk period-200MHz TmrClk input frequency-266MHz TmrClk period-266MHz TmrClk input high time TmrClk input low time HDLCEXTxClk, HDLCEXRxClk Notes: 1. TOPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 33.33 MHz for 133MHz parts, 50 MHz for 200MHz parts, and 66.66MHz for 266MHz parts. Min - 400 160 160 2.5 40 35% of nominal period 35% of nominal period 2.5 40 35% of nominal period 35% of nominal period - 30 - 20 - 15 45% of nominal period 45% of nominal period - 2TOPB + 2 TOPB + 1 TOPB + 1 - 30 - 20 - 15 40% of nominal period 40% of nominal period 0 Max 2.5 - - - 25 400 - - 25 400 - - 33.33 - 50 - 66.66 - 55% of nominal period 55% of nominal period 1000/(2TOPB + 2ns) - - - 33.33 - 50 - 66.66 - 60% of nominal period 60% of nominal period 8.192 Units MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns MHz ns MHz ns ns ns MHz ns ns ns MHz ns MHz ns MHz ns ns ns MHz
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Input Setup and Hold Waveform
SysClk 1.5V TIS MIN Inputs 1.5 V
TIH MIN
Valid
Output Delay and Float Timing Waveform
SysClk
1.5V TOV MAX TOH MIN
Outputs
1.5V Valid MAX MIN
TOF
Outputs
1.5V
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
I/O Specifications--All
Input (ns) Signal Output (ns) Hold Time (TOH min) async async n/a n/a n/a async n/a async n/a async n/a n/a n/a async n/a async n/a async n/a n/a n/a n/a async n/a n/a async n/a n/a 1.7 n/a n/a async Output Current (mA) I/O H I/O L (maximum) (minimum) 17 17 n/a n/a n/a 12 n/a 12 n/a 12 n/a n/a n/a 12 n/a 12 n/a 12 n/a n/a n/a n/a 12 n/a n/a 12 n/a n/a 12 12 n/a n/a 11 11 n/a n/a n/a 8 n/a 8 n/a 8 n/a n/a n/a 8 n/a 8 n/a 8 n/a n/a n/a n/a 8 n/a n/a 8 n/a n/a 8 8 n/a n/a Clock Notes
Setup Time Hold Time Valid Delay (TIS min) TIH min) (TOV max) async async async async async n/a async n/a async n/a async [async] async n/a [async] n/a async n/a async async async async n/a async async async async n/a n/a n/a dc n/a async async async async async n/a async n/a async n/a async [async] async n/a [async] n/a async n/a async async async async n/a async async async async n/a n/a n/a dc n/a async async n/a n/a n/a async n/a async n/a async n/a n/a n/a async n/a async n/a async n/a n/a n/a n/a async n/a n/a async n/a n/a 5.5 n/a n/a async
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_CTS [UART1_DCD] UART1_DSR UART1_DTR [UART1_RI] UART1_RTS UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
[IRQ0:6] JTAG Interface TCK TDI TDO TMS TRST
System Interface
GPIO30 Halt SysClk SysErr SysReset TestEn TmrClk
46
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
I/O Specifications--133 and 200MHz
(Part 1 of 2) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Output (ns) Hold Time (TOH min) 1.5 1.2 3.0 [2.3] [1.7] 2.9 [2.3] [1.7] 2.9[2.4] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 3.3 n/a 3.5 3.8 1.2 1.2 1.2 1.0 1.0 1.0 Output Current (mA) I/O H I/O L (maximum) (minimum) 12 12 12 8 8 8 EMC0MDClk PHYTX Clock Notes Setup Time Hold Time Valid Delay (TIS min) TIH min) (TOV max) n/a n/a n/a n/a n/a n/a 7.4 8.8 10.5 [7.3] [5.0] 11.8 [7.2] [5.6] 11.8[7.4] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 10.5 n/a 11.3 11.8 11.2 7.0 7.0 6.5 6.4 6.4
Ethernet Interface
EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1] [EMC0Tx0:1D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:1D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] 1, async 1 1
n/a n/a async[0.2] async[0.1] n/a 1.5 [0.8] [0.9] 1.3[0.7] 1.3[0.7] n/a n/a 23.8 24.2 n/a n/a 20.3 n/a n/a n/a n/a n/a n/a n/a n/a
n/a n/a async[1.7] async[1.9] n/a 1.7 [1.7] [0.3] 1.7[1.7] 1.8[1.9] n/a n/a 2.1 1.1 n/a n/a 1.0 n/a n/a n/a n/a n/a n/a n/a n/a
12 12 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 12 n/a 12 12 12 12 12 12 12 12
8 8 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 8 n/a 8 8 8 8 8 8 8 8
PHYTX PHYTX
1 1 1 1 1, async
PHYRX PHYRX PHYRX
1 1 1 1, async
HDLCEX Interface
HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA] [HDLCEXTxEnB]]
Trace Interface
[TrcClk]GPIO00 [TS1E]GPIO01 [TS2E]GPIO02 [TS1O]GPIO03 [TS2O]GPIO04 [TS3:6]GPIO05:08
47
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
I/O Specifications--133 and 200MHz
(Part 2 of 2) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Output (ns) Hold Time (TOH min) 1.5 1.0 1.4 1.0 1.0 1.0 1.0 1.4 -1.2 1.0 1.6 1.4 [1.1] [1.1] [1.2] 0.9 1.4 1.3 1.0 1.4 0.9 1.4 n/a 1.3 -0.9 n/a [1.3] Output Current (mA) I/O H I/O L (maximum) (minimum) 19 19 19 40 19 19 19 19 19 19 19 19 n/a 12 12 17 12 12 17 12 17 12 n/a 12 17 n/a 12 12 12 12 25 12 12 12 12 12 12 12 12 n/a 8 8 11 8 8 11 8 11 8 n/a 8 11 n/a 8 Clock Notes Setup Time Hold Time Valid Delay (TIS min) TIH min) (TOV max) n/a n/a n/a n/a n/a n/a 2.0 n/a n/a 2.0 n/a n/a [4.8] n/a [4.3] n/a n/a n/a 4.8 n/a 3.1 n/a 7.5 n/a n/a 4.0 n/a n/a n/a n/a n/a n/a n/a 0.3 n/a n/a 0.3 n/a n/a [0.0] n/a [-0.1] n/a n/a n/a 1.0 n/a 0.0 n/a -0.5 n/a n/a -0.6 n/a 7.2 5.8 7.0 4.9 5.9 5.9 5.7 7.2 0.4 5.6 7.4 7.1 [7.0] [7.5] [8.5] 8.5 7.4 7.2 9.3 7.6 8.3 7.5 n/a 7.5 0.5 n/a [8.3]
SDRAM Interface
BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemClkOut0:1 MemData00:31 RAS WE [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0:3 PerData00:15 PerOE PerPar0:1 PerR/W PerReady PerWBE0:1 PerClk PerErr [PerWE] SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 5 2, 3 3 2, 3 3 3 3 3 2, 3 3, 4 3 2, 3 2, 3
External Peripheral Bus Interface
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
I/O Specifications--266MHz
(Part 1 of 2) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (TIS min) TIH min) n/a n/a n/a n/a n/a n/a Output (ns) Valid Delay (TOV max) 7.4 6.7 7.7 [5.6] [4.6] 9.4 [5.5] [4.2] 9.4[5.7] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 7.6 n/a [8.5] [8.9] Hold Time (TOH min) 1.5 1.2 3 [2.3] [1.7] 2.9 [2.3] [1.7] 2.9[2.4] n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 3.3 n/a [3.5] [3.8] Output Current (mA) I/O H I/O L (maximum) (minimum) 12 12 12 8 8 8 EMC0MDClk PHYTX Clock Notes
Ethernet Interface
EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1 [EMC0Tx0:1D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] PHY0Col[PHY0Rx1Er]l PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:1D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] 1, async 1 1
n/a n/a async[0.1] async[0.1] n/a 1.5 [0.8] [0.8] 1.3[0.7] 1.3[0.7] n/a n/a 23.9 24.2 n/a n/a 24.2 n/a n/a
n/a n/a async[1.4] async[1.5] n/a 1.4 [1.3] [0.2] 1.3[1.3] 1.4[1.5] n/a n/a 1.6 0.8 n/a n/a 0.8 n/a n/a
12 12 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 12 n/a 12 12
8 8 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 8 n/a 8 8
PHYTX PHYTX
1 1 1 1 1, async
PHYRX PHYRX PHYRX
1 1 1 1, async
HDLCEX Interface
HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA] [HDLCEXTxEnB]
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
I/O Specifications--266MHz
(Part 2 of 2) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. Output times in table are in cycle 1. 3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (TIS min) TIH min) n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 1.8 n/a n/a 1.8 n/a n/a 4.1 n/a 3.7 n/a n/a n/a 3.9 n/a 2.7 n/a 6.2 n/a n/a 3.5 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0.3 n/a n/a 0.3 n/a n/a 0 n/a -0.1 n/a n/a n/a 1 n/a 0 n/a -0.5 n/a n/a -0.6 n/a Output (ns) Valid Delay (TOV max) 8.7 5.8 5.7 5.3 5.3 5.4 5.5 4.6 5.3 3.9 4.7 4.7 4.5 5.5 0.4 4.4 5.7 5.4 5.5 5.9 6.7 6.5 5.6 5.5 7.1 5.7 6.4 5.7 n/a 5.7 0.5 n/a 7 Hold Time (TOH min) 1.2 1.2 1.2 1 1 1 1.5 1 1.4 1 1 1 1 1.4 -1.2 1 1.6 1.4 1.1 1.1 1.2 0.9 1.4 1.3 1 1.4 0.9 1.4 n/a 1.3 -0.9 n/a 1.3 Output Current (mA) I/O H I/O L (maximum) (minimum) 12 12 12 12 12 12 19 19 19 40 19 19 19 19 19 19 19 19 n/a 12 12 17 12 12 17 12 17 12 n/a 12 17 n/a 12 8 8 8 8 8 8 12 12 12 25 12 12 12 12 12 12 12 12 n/a 8 8 11 8 8 11 8 11 8 n/a 8 11 n/a 8 SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 4 1, 2 2 1, 2 2 2 2 2 1, 2 2, 3 2 1, 2 1, 2 Clock Notes
Trace Interface
[TrcClk] [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6]
SDRAM Interface
BA1:0 BankSe3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemClkOut0:1 MemData00:31 RAS WE [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0:3 PerData00:15 PerOE PerPar0:1 PerR/W PerReady PerWBE0:1 PerClk PerErr [PerWE]
External Peripheral Bus Interface
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Initialization
The following describes the method by which initial chip settings are established when a system reset occurs. Strapping While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial conditions prior to NPe405L start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V or 10k to +5V, the recommended pull-down is 1k to GND.These pins are used for strap functions only during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options.
Strapping Pin Assignments
Function EXT_BootW Width of boot device on EBC data bus 8 bits 16 bits ZMII_Mode Ethernet ZMII mode MII mode SMII mode RMII 10 Mbps mode RMII 100 Mbps mode Option Ball Strapping Y21 (UART1_Tx) 0 1 V21 U20 (UART1_RTS) (UART1_DTR) 0 0 1 1 0 1 0 1
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
(c) Copyright International Business Machines Corporation 1999, 2002
All Rights Reserved Printed in the United States of America, October 2, 2002 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: Blue Logic IBM PowerPC CodePack CoreConnect IBM Logo PowerNP
Other company, product, and service names may be trademarks or service marks of others. Preliminary Edition (October 2, 2002) This document contains information on a new product under development by IBM. IBM reserves the right to change or discontinue this product without notice. This document is a preliminary edition of the PowerNP NPe405L data sheet. Make sure you are using the correct edition for the level of the product. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52 Hopewell Junction, NY 12533-6351 The IBM home page is www. ibm.com. The IBM Microelectronics Division home is www.chips.ibm.com. SA14-2558-10
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